Ferroelectric memory devices have been proposed as alternatives to conventional memory devices. Ferroelectric memory devices utilize the spontaneous polarization properties of ferroelectric films to provide data storage elements which offer relatively fast read/write operations compared with conventional storage elements. In addition, using a capacitor having a ferroelectric dielectric as a data storage device for a memory cell can reduce the power consumption of the memory cell and increase operational speed as refresh operations typically are not required to maintain data in the capacitor. Moreover, such a ferroelectric random access memory (FRAM) device may operate from a single power supply voltage.
Generally, two types of FRAM cells are conventionally used: (1) a transistor employing a ferroelectric film as a gate insulation film, and (2) an access transistor connected to a cell capacitor employing a ferroelectric film as a dielectric. Fabrication difficulties associated with the first type of cell include the potential formation of a silicon oxide film by reaction of silicon with oxygen atoms at the interface between the silicon channel region of the transistor and the ferroelectric gate insulation film. In addition, it may be difficult to form a high-quality ferroelectric film due to a lattice constant difference or thermal expansion coefficient difference between the silicon substrate and ferroelectric film.
For these reasons, conventional FRAM devices tend to employ the second structure described above. Lead zirconate titanate (PZT or PbZr.sub.x Ti.sub.1-x O.sub.3) is typically used for the dielectric of the capacitor. According to a typical fabrication process, PZT is deposited by sol-gel coating a metal electrode and then annealing the coating in an oxygen atmosphere at a temperature ranging from 500.about.650.degree. C., thereby forming a PZT layer on the electrode having an appropriate polarization characteristic. The annealing temperature of 500.degree. C. to 650.degree. C. may deform a conventional aluminum electrode, while using a tungsten electrode may reduce the dielectric ratio of the capacitor and the conductivity of the electrode due to oxidation of tungsten during the annealing of the PZT dielectric. Therefore, the PZT dielectric typically is formed on an electrode formed of a material, for example, platinum, having an oxidation resistance and a high melting point to obtain superior characteristics as a capacitor.
FIGS. 1 and 2 illustrate a conventional FRAM cell layout. Referring to FIG. 1, the conventional cell layout includes an active region 112 generally disposed along a direction x, and first and second word lines 130a, 130b disposed in parallel along a direction y transverse to the active region 112. The first and second word lines 130a, 130b divide the active region 112 into three sections, including a first source/drain region 118 adjacent the first word line 130a, a second source/drain region 117 positioned between the first and second word lines 130a, 130b, and a third source/drain region 116 adjacent the second word line 130b. A pair of lower electrodes 122a, 122b are disposed adjacent to the first and third source/drain regions 118, 116. A pair of upper electrodes 126a, 126b are disposed on an area of the respective lower electrodes 122a, 122b. First contact holes 112a, 112b expose predetermined areas of the respective first and third source/drain regions 118, 116. Second contact holes 132a, 132b expose a predetermined area of the lower electrodes 122a, 122b, and are adjacent respective upper electrodes 126a, 126b. A first interconnection 123a connects the first source/drain region 118 to the lower electrode 122a through the first and second contact holes 112a, 132a. A second interconnection 123b connects the third source/drain region 116 to the lower electrode 122b through the first and second contact holes 112b, 132b, A third contact hole 140a exposes an area of the second source/drain region 117, with a bit line 140 being connected to the second source/drain region 117 through the third contact hole 140a. Fourth contact holes 150a, 150b expose the upper electrodes 126a, 126b, with a first upper electrode line 150a connecting to the upper electrode 126a through the fourth contact hole 150a, and a second upper electrode line 155b connecting to the upper electrode 126b through the fourth contact hole 150b.
Referring to FIG. 2, the conventional FRAM includes a semiconductor substrate 116 having an active region and a nonactive region defined thereon by a field oxide layer 114. The first word line 130a is formed on a predetermined area of the active region and functions as a gate electrode. The first source/drain region 118 and the second source/drain region 117 are formed in the substrate 116 on opposite sides of the first word line 130a. A first interlayer insulation layer 500 is formed over the first source/drain region 118, the second source/drain region 117 and the first word line 130a. A capacitor including a lower electrode 122a, a ferroelectric film 124, and the upper electrode 126a, is formed on an area of the first interlayer insulation layer 500. Typically, the lower electrode 122a is platinum, and the ferroelectric film 124 is PZT.
A second interlayer insulation layer 600 is formed on the capacitor and first interlayer insulation layer 500, partially exposing the lower electrode 122a and the upper electrode 126a. A first interconnection 123a is formed on a predetermined area of the second interlayer insulation layer 600 and is electrically connected to the lower electrode 122a through the contact hole 132a and to the first source/drain region 118 through the contact hole 112a. A bit line 140 is connected to the second source/drain region 117 through the contact hole 140a. A third interlayer insulation layer 700 is formed covering the bit line 140 and the first interconnection 123a. A first upper electrode line 155a is connected to the upper electrode 126a through the contact hole 150a.
For the conventional FRAM cell illustrated, directly connecting the platinum lower electrode 122a to the silicon first source/drain region 118 may cause the electrode to lose conductivity or cause substitution of silicon in the substrate. To prevent this, the first source/drain region 118 and the lower electrode 122a are connected via the first interconnection 123a. However, it is difficult to reduce cell area using such a structure, generally making such an interconnection structure unsuitable for forming highly-integrated FRAM devices.